The so-called “silicon revolution” brought about the development of faster and larger computers beginning in the early 1960's with predictions of rapid growth because of the increasing numbers of transistors packed into integrated circuits with estimates they would double every two years. Since 1975, however, they doubled about every 18 months.
An active period of innovation in the 1970's followed in the areas of circuit design, chip architecture, design aids, processes, tools, testing, manufacturing architecture, and manufacturing discipline. The combination of these disciplines brought about the VLSI era and the ability to mass-produce chips with 100,000 transistors per chip at the end of the 1980's, succeeding the large scale Integration (“LSI”) era of the 1970's with only 1,000 transistors per chip. (Carre, H. et al. “Semiconductor Manufacturing Technology at IBM”, IBM J. RES. DEVELOP., VOL. 26, no. 5, September 1982). Mescia et al. also describe the industrial scale manufacture of these VLSI devices. (Mescia, N.C. et al. “Plant Automation in a Structured Distributed System Environment,” IBM J. RES. DEVELOP., VOL. 26, no. 4, July 1982).
The release of IBM's Power6™ chip in 2007, noted “miniaturization has allowed chipmakers to make chips faster by cramming more transistors on a single slice of silicon, to the point where high-end processors have hundreds of millions of transistors. But the process also tends to make chips run hotter, and engineers have been trying to figure out how to keep shrinking chips down while avoiding them frying their own circuitry.” (http://www.nytimes.com/reuters/technology/tech-ibm-power.html?pagewanted=print (Jul. 7, 2006))
Technology scaling of semiconductor devices to 90 nm and below has provided many benefits in the field of microelectronics, but has introduced new considerations as well. While smaller chip geometries result in higher levels of on-chip integration and performance, higher current and power densities, increased leakage currents, and low-k dielectrics with poorer heat conductivity occur that present new challenges to package and heat dissipation designs.
Thus CMOS power density is increasing. Recently the industry has seen it rise from100 W/sq cm to 200 W/sq cm, beyond that of bipolar technology in the early 1990's. This increase in power density also increases the operating temperature of the device.
Compliant heat sinks which cover more than one semiconductor chip on a multi-chip module (MCM) have often been proposed as a cooling solution for such modules. As there is generally a mismatch between the coefficient of thermal expansion (CTE) of the heat sink and the MCM, shear stress and/or strain can develop in the interface between the heat sink and the chips, as the “compliant” heat sinks generally are only significantly compliant in the vertical (perpendicular to the chip faces) direction to accommodate chip tilt and/or height mismatch. This stress and/or strain is typically absorbed by a low-modulus thermal interface material (TIM) used to connect the heat sink to the chips on the MCM.
These “compliant” heat sinks generally are not significantly compliant in the horizontal (parallel to the chip faces) direction and as a result do not adequately address shear stress and/or strain developed horizontally in the interface between the heat sink and the chips.
When a rigid or semi-rigid TIM such as a stiff gel, Indium, or solder is used as a heat sink, it can fail under thermal cycling due to this stress/strain. Thermal greases employed to connect chip components to conventional heat sinks heat sinks do not provide a complete solution to the problem since their heat conductivity is at best about 4.5 W/m K. These greases function by loading thermally conducting particles such as copper, silver, carbon nanotubes or other materials into the grease to lower its inherent thermal resistance, however, a common problem of this approach lies in effecting thermal conduction between the particles via proximity of the particles to one another. The particles are neither chemically nor metallurgically bonded to one another therefore high thermal resistance is invariably present in these interface materials. The TIM material typically would sit underneath “contact patches,” in the device being cooled, helping to thermally bridge the gap between the device and the “contact patches” Movement of the two surfaces interfacing with the grease therefore can “pump” the grease out of the interface, resulting in failure of the interface.